Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 20 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11.5 JESD204A serializer
For more information about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
Fig 20. CML output connection to the receiver (AC-coupled)
CMLPA/CMLPB
CMLNA/CMLNB
12 mA to 26 mA
100 Ω
50 Ω
10 nF
10 nF
005aaa08
3
VDDD
−
+
RECEIVER
Fig 21. General overview of the JESD204A serializer
FRAME
TO
OCTETS
F octets
SCRAMBLER
TX transport layer
CF: position of control bits
HD: frame boundary break
Padding with Tail bits (TT)
Mx(N'xS) bits Lx(F) octets L octets
N' = N+CS
S samples per frame cycle
samples stream to
lane stream mapping
N bits from Cr
0
+
CS bits for control
N bits from Cr
M−1
+
CS bits for control
M CONVERTERS L LANES
LANE 1
FRAME
TO
OCTETS
F octets
SCRAMBLER
8-bit/
10-bit
SER
TX CONTROLLER
LANE 0
8-bit/
10-bit
SER
ALIGNMENT
CHARACTER
GENERATOR
ALIGNMENT
CHARACTER
GENERATOR
SYNC~
005aaa084