Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 2 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number Sampling
frequency
(Msps)
Package
Name Description Version
ADC1113D125HN/C1 125 HVQFN56 plastic thermal enhanced very thin quad flat package;
no leads; 56 terminals; body 8 × 8 × 0.85 mm
SOT684-7
Fig 1. Block diagram
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
ADC A CORE
11-BIT
PIPELINED
T/H
INPUT
STAGE
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC B CORE
11-BIT
PIPELINED
T/H
INPUT
STAGE
ADC1113D
DLL
PLL
FRAME ASSEMBLY
SERIALIZER A
SPI
OUTPUT
BUFFER A
SERIALIZER B
OUTPUT
BUFFER B
SCRAMBLER A
ENCODER 8-bit/10-bit A
SCRAMBLER B
ENCODER 8-bit/10-bit B
8-bit 8-bit
INAP
INAM
CLKP
CLKM
INBP
SCRAMBLER RESET
INBM
8-bit8-bit 10-bit
10-bit
SWING_n
SWING_n
SYNCP
SCLK
CFG (0 to 3) SDIO
CS
SYNCN
CMLNB
CMLPB
CMLNA
CMLPA
OTR
D11 to D0
D11 to D0
OTR
005aaa165
REFAT
REFAB
REFBB
REFBT
VCMA
VREF
SENSE
VCMB