Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 18 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via 5 kΩ internal resistors.
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 17. Differential clock input
Sine
clock input
CLKP
CLKM
005aaa17
3
Sine
clock input
CLKP
CLKM
005aaa05
4
LVPECL
clock input
005aaa17
2
CLKP
CLKM
V
cm(clk)
= common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
CLKP
CLKM
005aaa08
1
5 kΩ 5 kΩ
V
cm(clk)
SE_SEL SE_SEL
package ESD parasitics