Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 17 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11.2.3 Common-mode output voltage (V
O(cm)
)
An 0.1 μF filter capacitor should be connected between the pins VCMA and VCMB and
ground to ensure a low-noise common-mode output voltage. When AC-coupled, these
pins can be used to set the common-mode reference for the analog inputs, for instance
via a transformer middle point.
11.2.4 Biasing
The common-mode input voltage, V
I(cm)
, at the inputs to the sample-and-hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
11.3 Clock input
11.3.1 Drive modes
The ADC1113D125 can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 15. Reference equivalent schematic
1.5 V
VCMA
VCMB
0.1 μF
PACKAGE ESD PARASITICS
005aaa07
7
COMMON MODE
REFERENCE
ADC CORE
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
LVCMOS
clock input
CLKP
CLKM
005aaa17
4
005aaa05
3
LVCMOS
clock input
CLKP
CLKM