Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 12 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1113D125 supports a differential or a single-ended input
drive. Optimal performance is achieved using differential inputs with the common-mode
input voltage (V
I(cm)
) on pins INP and INM set to 0.5VDDA.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2
and Table 21).
Figure 6
shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (R-C filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 6. Input sampling circuit
005aaa06
9
INAP
INBP
package ESD parasitics
switch
R
on
= 15 Ω
4 pF
4 pF
C
s
C
s
switch
R
on
= 15 Ω
INAM
INBM
1, 14
2, 13
internal
clock
internal
clock