Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 10 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
10.2 Clock and digital output timing
[1] Typical values measured at V
DDA
=3V, V
DDD
= 1.8 V, T
amb
=25°C. Minimum and maximum values are across the full temperature
range T
amb
= −40 °C to +85 °C at V
DDA
=3V, V
DDD
= 1.8 V; V
I
(INAP, INBP) − V
I
(INAM, INBM) = −1 dBFS; internal reference mode;
100 W differential applied to serial outputs; unless otherwise specified.
10.3 Serial output timing
The eye diagram of the serial output is shown in Figure 3 and Figure 4. Test conditions
are:
• 3.125 Gbps data rate
• T
amb
=25°C
• DC coupling with two different receiver common-mode voltages
Table 7. Characteristics
[1]
Symbol Parameter Conditions Min Typ Max Unit
Clock timing input: pins CLKP and CLKM
f
clk
clock frequency 100 - 125 Msps
t
lat(data)
data latency time - 14 - clock cycle
δ
clk
clock duty cycle DCS_EN = logic 1 30 50 70 %
DCS_EN = logic 0 45 50 55 %
t
d(s)
sampling delay time - 0.8 - ns
t
wake
wake-up time - 76 - μs
Fig 3. Eye diagram at 1 V receiver common-mode
005aaa08
8