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1. General description

The ADC1113D125 is a dual-channel 11-bit Analog-to-Digital Converter (ADC) optimized

for high dynamic performance and low power at a sample rate of 125 Msps. Pipelined

architecture and output error correction ensure the ADC1113D125 is accurate enough to

guarantee zero missing codes over the entire operating range. Supplied from a 3 V

source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.

Each lane is differential and complies with the JESD204A format. An integrated Serial

Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC

configurations is also available via the binary level control pins taken, which are used at

power-up. The device also includes a programmable full-scale SPI to allow flexible input

voltage range of 1 V to 2 V (peak-to-peak).

Excellent dynamic performance is maintained from the baseband to input frequencies of

170 MHz or more, making the ADC1113D125 ideal for use in communications, imaging,

and medical applications.

2. Features and benefits

3. Applications

ADC1113D125

Dual 11-bit ADC; serial JESD204A interface

Rev. 3 — 10 February 2011 Product data sheet

 SNR, 66.5 dBFS; SFDR, 86 dBc  Input bandwidth, 600 MHz

 Sample rate: 125 Msps  Power dissipation, 1270 mW

 Clock input divided by 2 for less jitter

contribution

 SPI register programming

 3 V, 1.8 V single supplies  Duty Cycle Stabilizer (DCS)

 Flexible input voltage range:

1V(p-p)to2V(p-p)

 High IF capability

 Two configurable serial outputs  Offset binary, two’s complement, gray

code

 Two JESD204A serial outputs  Power-down mode and Sleep mode

 Pin compatible with ADC1613D series,

ADC1413D series, and

ADC1213D series

 HVQFN56 package

 Wireless and wired broadband

communications

 Portable instrumentation

 Spectral analysis  Imaging systems

 Ultrasound equipment  Software defined radio

Summary of content (41 pages)

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ADC1113D125 Dual 11-bit ADC; serial JESD204A interface Rev. 3 — 10 February 2011 Product data sheet 1. General description The ADC1113D125 is a dual-channel 11-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power at a sample rate of 125 Msps. Pipelined architecture and output error correction ensure the ADC1113D125 is accurate enough to guarantee zero missing codes over the entire operating range. Supplied from a 3 V source for analog and a 1.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 4. Ordering information Table 1. Ordering information Type number ADC1113D125HN/C1 Sampling frequency (Msps) Package Name Description 125 HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-7 no leads; 56 terminals; body 8 × 8 × 0.85 mm Version 5.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 6. Pinning information 43 SYNCP 44 SYNCN 45 DGND 46 VDDD 47 SWING_0 48 SWING_1 49 DNC 50 VDDA 51 AGND 52 AGND 53 VDDA 54 SENSE 55 VREF 56 VDDA 6.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface ADC1113D125 Product data sheet Table 2.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 2. Pin description …continued Symbol Pin Type [1] Description VDDA 53 P analog power supply 3 V SENSE 54 I reference programming pin VREF 55 I/O voltage reference input/output VDDA 56 P analog power supply 3 V [1] P: power supply; G: ground; I: input; O: output; I/O: input/output. [2] OTRA stands for “OuT of Range” A. OTRB stands for “OuT of Range” B. 7. Limiting values Table 3.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 9. Static characteristics Table 5. Symbol Static characteristics[1] Parameter Conditions Min Typ Max Unit 2.85 3.0 3.4 V Supplies VDDA analog supply voltage VDDD digital supply voltage 1.65 1.8 1.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 5. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit Analog inputs: pins INAP, INAM, INBP, and INBM II input current track mode −5 - +5 μA RI input resistance track mode - 15 - Ω CI input capacitance track mode - 5 - pF VI(cm) common-mode input voltage track mode 0.9 1.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 5. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit Serial configuration: pins SYNCCP, SYNCCN VIL LOW-level input voltage differential; input - 0.95 - V VIH HIGH-level input voltage differential; input - 1.47 - V INL integral non-linearity −5 - +5 LSB DNL differential non-linearity −0.95 ±0.25 +0.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 10. Dynamic characteristics 10.1 Dynamic characteristics Table 6.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 10.2 Clock and digital output timing Table 7. Characteristics[1] Symbol Parameter Conditions Min Typ Max Unit 100 - 125 Msps Clock timing input: pins CLKP and CLKM fclk clock frequency tlat(data) data latency time δclk clock duty cycle - 14 - clock cycle DCS_EN = logic 1 30 50 70 % DCS_EN = logic 0 45 50 55 % td(s) sampling delay time - 0.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 005aaa089 Fig 4. Eye diagram at 2 V receiver common-mode 10.4 SPI timing Table 8.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 11. Application information 11.1 Analog inputs 11.1.1 Input stage description The analog input of the ADC1113D125 supports a differential or a single-ended input drive. Optimal performance is achieved using differential inputs with the common-mode input voltage (VI(cm)) on pins INP and INM set to 0.5VDDA.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface INPA/ INBP R C INAM/ INBM R 001aan679 Fig 7. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 9. RC coupling versus input frequency - typical values Input frequency (MHz) Resistance (Ω) Capacitance (pF) 3 25 12 70 12 8 170 12 8 11.1.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface ADT1-1WT Analog input 100 nF ADT1-1WT 50 Ω 12 Ω INAP INBP 50 Ω 8.2 pF 50 Ω 100 nF 50 Ω 12 Ω INAM INBM VCM 100 nF 100 nF 005aaa071 Fig 9. Dual transformer configuration The configuration shown in Figure 9 is recommended for high frequency applications. In both cases, the choice of transformer is a compromise between cost and performance. 11.2 System reference and power management 11.2.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface REFAT/ REFBT REFAB/ REFBB REFERENCE AMP VREF EXT_ref BUFFER EXT_ref BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 001aan670 Fig 10. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 10. Table 10.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa117 005aaa116 Fig 11. Internal reference, 2 V (p-p) full-scale Fig 12. Internal reference, 1 V (p-p) full-scale VREF VREF V 0.1 μF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa118 005aaa119 Fig 13. External reference, 1 V (p-p) to 2 V (p-p) full-scale Fig 14.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 11.2.3 Common-mode output voltage (VO(cm)) An 0.1 μF filter capacitor should be connected between the pins VCMA and VCMB and ground to ensure a low-noise common-mode output voltage. When AC-coupled, these pins can be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. PACKAGE ESD PARASITICS COMMON MODE REFERENCE 1.5 V VCMA VCMB 0.1 μF ADC CORE 005aaa077 Fig 15.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Sine clock input CLKP Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVPECL clock input CLKM 005aaa172 c. LVPECL clock input Fig 17. Differential clock input 11.3.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 18.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL accordingly, the unused pin should be connected to ground via a capacitor. 11.3.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface VDDD 50 Ω CMLPA/CMLPB 10 nF CMLNA/CMLNB − + 100 Ω RECEIVER 10 nF 12 mA to 26 mA 005aaa083 Fig 20. CML output connection to the receiver (AC-coupled) 11.5 JESD204A serializer For more information about the JESD204A standard refer to the JEDEC web site. 11.5.1 Digital JESD204A formatter The block placed after the ADC cores is used to implement all functionalities of the JESD204A standard.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface ADC_MODE[1:0] PRBS DUMMY SCR_IN_MODE[1:0] 11 11 + 1 10 11 + 1 N & CS LANE_MODE[1:0] 8 N + CS 11 + 1 8-bit/ 10-bit SCR PRBS ADC_PD ADC A 00 01 ×1 frame CLK ×F character CLK × 10F FRAME ASSEMBLY bit CLK FSM (frame assembly character replication ILA test mode) 11 + 1 '0' 01 '0/1' 10 PRBS 11 PRBS 11 PRBS 11 + 1 10 11 + 1 N & CS 01 '0/1' 10 '0' 01 8-bit/ 10-bit SCR N + CS 8 SER 10 00 LA
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 13. Output codes VINP − VINM Offset binary Two’s complement OTR pin +0.9970703 111 1111 1100 011 1111 1100 0 +0.9980469 111 1111 1101 011 1111 1101 0 +0.9990234 111 1111 1110 011 1111 1110 0 +1.0000000 111 1111 1111 011 1111 1111 0 > +1 111 1111 1111 011 1111 1111 1 11.6 Serial Peripheral Interface (SPI) 11.6.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface The steps involved in a data transfer are as follows: 1. The falling edge on pin CS in combination with a rising edge on pin SCLK determine the start of communications. 2. The first phase is the transfer of the 2-byte instruction. 3. The second phase is the transfer of the data which can vary in length but is always a multiple of 8 bits. The MSB is always sent first (for instruction and data bytes). 4.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 11.6.3 Register description 11.6.3.1 ADC control registers Table 18. Register Channel Index (address 0003h) Default values are highlighted. Bit Symbol Access Value Description 7 to 2 - - 111111 not used 1 ADCB R/W 0 ADCA ADC B gets the next SPI command: 0 ADC B not selected 1 ADC B selected R/W ADC A gets the next SPI command: 0 ADC A not selected 1 ADC A selected Table 19.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 21. Register Vref (address 0008h) Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 INTREF_EN R/W 2 to 0 INTREF[2:0] enable internal programmable VREF mode: 0 disable 1 active R/W programmable internal reference: 000 0 dB (FS=2 V) 001 −1 dB (FS=1.78 V) 010 −2 dB (FS=1.59 V) 011 −3 dB (FS=1.42 V) 100 −4 dB (FS=1.26 V) 101 −5 dB (FS=1.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 24. Register Test pattern 2 (address 0015h) Default values are highlighted. Bit Symbol Access Value Description 7 to 0 TESTPAT_2[10:3] R/W 00000000 custom digital test pattern (bit 10 to 3) Table 25. Register Test pattern 3 (address 0016h) Default values are highlighted. Bit Symbol Access Value Description 7 to 0 TESTPAT_3[2:0] R/W 00000000 custom digital test pattern (bit 2 to 0) 11.6.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 28. Ser_Cfg_Setup (address 0803h) Default values are highlighted. Bit Symbol Access Value Description 7 to 4 - - 0000 not used 3 to 0 CFG_SETUP[3:0] R/W 1000 quick configuration of JESD204A. These settings overrule the configuration of pins CFG3 to CFG0 (see Table 29). Table 29.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 30. Ser_Control1 (address 0805h) Default values are highlighted. Bit Symbol 7 6 5 4 Access Value Description - - 0 not used TRISTATE_CFG_PINS R/W 1 pins CFG3 to CFG0 are set to high-impedance. Switch to 0 automatically after start-up or reset.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 33. Ser_ScramblerA (address 0809h) Default values are highlighted. Bit Symbol Access Value Description 7 - - 0 not used 6 to 0 LSB_INIT[6:0] R/W 0000000 defines the initialization vector for the scrambler polynomial (lower) Table 34. Ser_ScramblerB (address 080Ah) Default values are highlighted.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 40. Cfg_5_K (address 0824h) Default values are highlighted. Bit Symbol Access Value Description 7 to 5 - - 000 not used 4 to 0 K[4:0] R/W 01000 defines the number of frames per multiframe, minus 1 Table 41. Cfg_6_M (address 0825h) Default values are highlighted. Bit Symbol Access Value Description 7 to 1 - - 0000000 not used 0 M R/W 0 defines the number of converters per device, minus 1 Table 42.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 47. Cfg_02_2_LID (address 082Dh) Default values are highlighted. Bit Symbol Access Value Description 7 to 5 - 4 to 0 LID[4:0] - 000 not used R/W 11100 defines lane 2 identification number Table 48. Cfg01_13_fchk (address 084Ch) Default values are highlighted.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 50. Lane0_0_ctrl (address 0870h) …continued Default values are highlighted. Bit Symbol Access 0 LANE_PD R/W Value Description lane power-down control: 0 lane is operational 1 lane is in Power-down mode Table 51. Lane2_0_ctrl (address 0871h) Default values are highlighted.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Table 52. ADCA_0_ctrl (address 0890h) Default values are highlighted.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 12. Package outline HVQFN56: plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm A B D SOT684-7 terminal 1 index area A E A1 c detail X e1 e 1/2 e L 15 28 14 C C A B C v w b y1 C y 29 e e2 Eh 1/2 e 1 42 terminal 1 index area 56 43 X Dh 0 2.5 scale Dimensions Unit A(1) A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 13. Abbreviations Table 54.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 14. Revision history Table 55. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1113D125 v.3 20110210 Product data sheet - ADC1113D125 v.2 Modifications: • • • • • Data sheet status changed from Preliminary to Product. Text and drawings updated throughout entire data sheet. Table 29 “JESD204A configuration table” added to Section 11.6.4. All tables in Section 11.6.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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ADC1113D125 NXP Semiconductors Dual 11-bit ADC; serial JESD204A interface 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.