Datasheet

Remark: as the clock can come either internally or externally, multiplexers are available so as to
route the right clock signal to the devices, the ADC1413D125 and the FPGA.
When using an external clock the double switch SW5 should be set to the “ON” position.
Fig 7. Clock Inputs
Clock signal
coming from
one generator
and fed to J19
and CLKP
Clock Generator
- PLL
- CML/LVDS
- Direct input
available