Quick Start ADC1x13D series demonstration Board Rev. 1.0 — April 2010 Quick Start Document information Info Content Keywords JESD204A, CGVTM, Demonstration board, ADC, Labview Abstract This document describes how to use the demonstration board for the Analog-to-digital converter ADC1613D, ADC1413D, ADC1213D and ADC1113D, JESD204A compliant.
Revision history Rev Date Description 0.1 2009.06.01 Initial version. 0.2 2009.07.22 First update version. 0.3 2009.03.01 SW update version.
1. Quick start 1.1 Setup overview Fig 1 presents the connections to measure the ADC1x13Dxxx DC Power supply for complete board (5V/2A) Output connector for parallel data INPUT-A Clock and signal Generator CLK-P CLK-N Optional : FPGA Clock inputs INPUT-B USB port for connection to PC (USB and SPI controller) Fig 1.
1.2 Essential Features of the Demonstration Board Fig 2.ADC1413D125 with 2 lanes in pairs of CML compliant differential Fig. 2 shows the ADC1413D125 in its environment. The output is a series CML connection capable of delivering a throughput rate of 3.125Gsps as specified by the JESD204A standard.
D11 lights up: FPGA has up-loaded its bit-stream Flash Memory D12 lights up: USB Host detected Mini USB connector Fig 4. On board memory with LED D11 indicating FPGA up-loaded and running and D12 indicating USB host detected Furthermore, after connecting the USB port and installing the driver, the LED D12 indicates that the USB host has been detected and is up and running. Push Button BP1 is a manual reset of the FPGA.
Fig 6. shows the LEDs D9-D16 which are used to indicate the status of the FPGA. D13 FPGA clk heart beat D14 Sync signal is active D15 K28.5 received D16 14 bits Data are reverted 8bits by 8 bits Fig 6. D13 – D16 indicates the status of the FPGA PUSH-A Perform a Manual Synchronization between FPGA and ADC PUSH-B Invert 14 bits parallel data Byte wise ( 8 bits by 8 bits) The SYNC signal is a synchronization signal used at the beginning of the transmission.
Clock Generator - PLL - CML/LVDS - Direct input available Fig 7. Clock signal coming from one generator and fed to J19 and CLKP Clock Inputs Remark: as the clock can come either internally or externally, multiplexers are available so as to route the right clock signal to the devices, the ADC1413D125 and the FPGA. When using an external clock the double switch SW5 should be set to the “ON” position.
2. Example 2.1 Setup example DC adaptor connected to mains SMA 100 A Rohde & Schwarz Signal Generator SMA 100 A Rohde & Schwarz Clock Generator Fig 9. ADC1413D125D Demonstrator Hardware set USB SPI ADC1413D125.
3. SPI quick start 3.1 Install The demonstration board is delivered with the following software: Labview Runtime: LabVIEW85RuntimeEngineFull.exe Labview executable: Andromeda.exe Appropriate drivers • Step 1 Connect the device to a USB port on your PC. Windows ‘Found New Hardware Wizard’ will be launched. Select ‘No, not this time’ from the options available and then click ‘Next’ to proceed with the installation.
• Step 2 Select ‘Install from a list or specific location (Advanced)’ as shown below and then click ‘Next’. • Step 3 Select ‘Search for the best driver in these locations’ and enter the file path of the folder CD-ROM CONTENT\CD-ROM2_ADC1213d_ADC1413d_DAC1408d\Version_1.0\Driver USB \driver_d2xx’ in the combo-box (‘C:\driver_2xx’ in the example below) or browse to it by clicking the browse button. Once the file path has been entered in the box, click ‘next’ to proceed.
• Step 4 Windows should then display a message indicating that the installation was successful. Click ‘Finish’ to complete the installation for the first port of the device.
3.2 SPI interface • Step 1 Install the LabVIEW Run-time Engine LabVIEW85RuntimeEngineFull.exe (if not already installed). • Step 2 Start the LabVIEW application “ADC1x13.exe”. a graphical window will pop-up Under the “ Write register from command file” field, choose the write configuration file from “ADC Command” directory depending on the used operating points. Click on the “read from config file”. Push the Push_A button on the board to make a manual synchronization of the JESD204A communication.
Click on ADC button to choose between internal ADC capture or FPGA capture Click on Load DATA to get the FFT and the ADC performances
Load Data to start capturing Select FFT without window (Clock coherency OK) Select the wanted ADC input channel. « latest MRA » button must be green Check input level here Select Input Frequency = 150M ADC clock = 76.8M Select « use coherence » when clock input coherence is OK in order to get SFDR value calculation SNR value (dbFS) Select SPI setting file then click “read config from file” in order to write SPI setting in the device.
