Datasheet

NXP Semiconductors
Quick start
Quick start ADC1412D, ADC1212D, ADC111
2D series
Quick start
QS_ADC1412D_10.doc
Rev. 10 — 17 December 2010
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3.2 ADC1412D LVDS outputs (demoboard F2/DB)
The figure 7 below shows an overview of the whole system ADC1412D+HSDC extension module with LVDS outputs configuration (e.g.
ADC1412D125F1/DB) for which connection is done with a bridge SAMTEC (HSDC-ACC05/DB), together with a supply extension module (HSDC-
ACC09/DB release B) for the ADC1412D demo-board:
Fig 7. Evaluation set-up measurement with ADC1412D125F2/DB and HSDC-EXTMOD01/DB
Note 1: make sure that supply extension release B is used: it delivers the 3 V supply for LVDS output path for the ADC.
Note 2: make sure that LVDS connection is done as shown.
USB
SPI
MODULE
P
RESENTED CONFIGURATION
. Single-ended clock on CLKP
. 2 V
pp
input full scale
. Binary LVDS outputs
C
LOCK SIGNAL
.
e.g 125 Msps
CLOCK
GENERATOR
R
EFERENCE SIGNAL
. e.g 170 MHz
SIGNAL
GENERATOR
+5V
POWER SUPPLY
. I = 3.2 A
USB
SPI
MODULE
+5
V
POWER SUPPLY
. I =
3.2
A
B
RIDGE
SAMTEC
. to connect LV
DS DDR data path