Quick start ADC1412D, ADC1212D, ADC1112D series Demonstration board for ADC1412D, ADC1212D, ADC1112D series Rev. 10 — 17 December 2010 Quick start Document information Info Content Keywords PCB2004-1, Demonstration board, ADC, Converter, ADC1412D, ADC1212D and ADC1112D series. Abstract This document describes how to use the demonstration board for the analog-to-digital converter ADC1412D, ADC1212D and ADC1112D series.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Revision history Rev Date Description 1 20081001 Initial version. 2 20090518 Update to PCB2004-1.2. 3 20090610 Add SPI software description. 4 20100518 Update to latest release of SPI software. Add HSDC extension module acquisition system description. 5 20100601 Correction added. 6 20100730 Update for LVDS acquisition mode. 7 20100806 Update to latest acquisition software tool.
NXP Semiconductors QS_ADC1412D_10.doc Quick start 1. Overview of the ADC1412D, ADC1212D, ADC1112D demo board 1.1 ADC1412D series Figure 1 presents the connections to measure the ADC1412D series: INPUT A SIGNAL . 2 Vpp sinewave . AC .GND POWER SUPPLY .1.8 V . I = 40 mA POWER SUPPLY . 3 V .GND . I = 370 mA SYNTHESIZED SIGNAL GENERATOR FILTER . High-order . Band pass LOGIC ANALYZER Output data ADC A (top to bottom): . DA13 (MSB) to DA0 (LSB) CLOCK SIGNAL . sinewave . AC .
NXP Semiconductors QS_ADC1412D_10.doc Quick start 1.2 ADC1212D series Figure 2 presents the connections to measure the ADC1212D series: INPUT A SIGNAL . 2 Vpp sinewave . AC .GND POWER SUPPLY .1.8 V . I = 40 mA POWER SUPPLY . 3 V .GND . I = 370 mA SYNTHESIZED SIGNAL GENERATOR FILTER . High-order . Band pass SYNTHESIZED SIGNAL GENERATOR LOGIC ANALYZER CLOCK SIGNAL . sinewave . AC . DAV for synchronization Output data ADC B (top to bottom): .
NXP Semiconductors QS_ADC1412D_10.doc Quick start 1.3 ADC1112D series Figure 3 presents the connections to measure the ADC1112D series: INPUT A SIGNAL . 2 Vpp sinewave . AC .GND POWER SUPPLY .1.8 V . I = 40 mA POWER SUPPLY . 3 V .GND . I = 370 mA SYNTHESIZED SIGNAL GENERATOR FILTER . High-order . Band pass SYNTHESIZED SIGNAL GENERATOR LOGIC ANALYZER CLOCK SIGNAL . sinewave . AC . DAV for synchronization Output data ADC B (top to bottom): .
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 1.4 Power supply The board is powered with a 3 VDC and 1.8/3 VDC power supplies. A power supply regulator is used to supply all the circuitry on the board. Table 1. General power supply Name Function View J8 +3 V green connector – Power supply 3 VDC / 400 mA. J7 +1.8 V green connector – Power supply 1.8 VDC / 100 mA TP1 AGND test point – Digital ground TP2 DGND test point – Analog ground TP1 TP2 J7 J8 1.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 1.6 Output signals (DA0 to DA13, DB0 to DB13, OTRA, DAV) The digital output signal is available in binary, 2’s complement or gray format. A Data Valid Output clock (DAV) is provided by the device for the data acquisition. Table 3.
NXP Semiconductors QS_ADC1412D_10.doc Quick start 2. HSDC extension module: acquisition board The figure 4 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board: RED LED FOR +3V3 POWER RED LED FOR POWER SUPPLY CONNECTION +5V POWER SUPPLY . I = 3.2 A JUMPER FOR I/O SUPPLY . define either I/O is 1.8 V or 3.3 V SIGNAL GENERATOR GREEN LED FOR EMBEDDED PLL LOCK STATUS CMOS I/O CONNECTOR .
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start The HSDC extension module is intended for acquisition/generation and clock generation purpose. When connected to an ADC demo-board it is intended as an acquisition system for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR (SAMTEC QTH_060_02 P2 connector).
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 5. HSDC extension module: HE14 CMOS hardware schematic overview QS_ADC1412D_10.doc Quick start © NXP B.V. 2010. All rights reserved. Rev.
NXP Semiconductors QS_ADC1412D_10.doc Quick start 3. Combo ADC1412D and HSDC extension module 3.1 ADC1412D CMOS outputs (demoboard F1/DB) The figure 6 below shows an overview of the whole system ADC1412D+HSDC extension module with CMOS outputs configuration (e.g. ADC1412D125F1/DB) for which connection is straightforward, together with a supply extension module (HSDC-ACC09/DB release A) for the ADC1412D demo-board: +5 V POWER SUPPLY . I = 3.2 A PRESENTED CONFIGURATION . Single-ended clock on CLKP .
NXP Semiconductors QS_ADC1412D_10.doc Quick start 3.2 ADC1412D LVDS outputs (demoboard F2/DB) The figure 7 below shows an overview of the whole system ADC1412D+HSDC extension module with LVDS outputs configuration (e.g. ADC1412D125F1/DB) for which connection is done with a bridge SAMTEC (HSDC-ACC05/DB), together with a supply extension module (HSDCACC09/DB release B) for the ADC1412D demo-board: +5 V POWER SUPPLY . I = 3.2 A BRIDGE SAMTEC . to connect LVDS DDR data path PRESENTED CONFIGURATION .
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 3.3 ADC Software tool Run the application “SW_ADC_1_r02.exe”. This application will allow: • the user to control features on our high speed ADC through the SPI interface available on any ADC1412D, ADC1212D and ADC1112D series; • as well as performing any online data acquisition to evaluate the performances of the ADC1412D, ADC1212D and ADC1112D series.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 9. SW_ADC_1_r02: “Info” page The HSDC-EXTMOD is not yet initialized, so the embedded PLL (LMK03001 in this example) is not locked. Initialization is only required for acquisition purpose. 3.3.1 ADC SPI programming Functional Registers page The page displays all SPI registers for ADC1412D, ADC1212D and ADC1112D series: Fig 10. SW_ADC_1_r02: “ADC - Functional Registers” page QS_ADC1412D_10.doc Quick start © NXP B.V.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Perform any settings and then click on the “Send data to device” button to update the device registers. 3.3.2 ADC SPI programming Read Registers page This page can be used to read all registers by clicking on the “Read all registers” button and will display the result in the table below: Fig 11. SW_ADC_1_r02: “ADC - Read Registers” page When all registers have been read, it is possible to save the data to a text file.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Column 1 Column 2 15 00 16 00 17 00 20 0e 21 00 22 00 Note that all data are saved in hexadecimal format. Click on the “Save registers read to file” button to select the file to store data to. Make sure that you store your file with “.txt” extension, this will allow you to re-use the file on the “ADC - Load Registers” page. 3.3.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Table 6.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 13. SW_ADC_1_r02: “ADC - Load Registers” page It is not necessary to have a file that has the whole set of registers listed. The only restriction is regarding the formatting of the file as given in section 3.3.2. Note: this page can not be used to download data saved during the comparison process.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 14. SW_ADC_1_r02: “Tools” page Note: The level of the harmonics shown does not reproduce the behavior of the ADC; they are only given as indication for location. 3.3.6 Acquisition page This page will acquire data to evaluate the high dynamic performance of the device: Fig 15. SW_ADC_1_r02: “Acquisition” page QS_ADC1412D_10.doc Quick start © NXP B.V. 2010. All rights reserved. Rev.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Before proceeding to any acquisition, the user needs to do the following entries: • the sampling frequency Fs: 80 Msps in our example (field ); • the input frequency Fin: 175 MHz in our example for both ADC channels (field ); • the number of samples to be acquired 16384 in our example (field ); • indicate whether it is CMOS or LVDS DDR (field ); • press the “INITIALIZATION” button .
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 16. SW_ADC_1_r02: “Acquisition” page, FFT graph Press the “Autoscale” button to display the whole content. 3.3.6.2 Reorganized signal The reorganized signal displays the reconstructed sine wave from coherency calculation corresponding to 1 period of the input signal: Fig 17. SW_ADC_1_r02: “Acquisition” page, reorganized signal graph QS_ADC1412D_10.doc Quick start © NXP B.V. 2010. All rights reserved. Rev.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Press the “Autoscale” button to display the whole content. 3.3.6.3 Unreconstruted signal The unreconstructed signal displays the unreconstructed sine wave corresponding to the whole number of period being acquired following the coherency rule: Zoom tool Fig 18. SW_ADC_1_r02: “Acquisition” page, unreconstructed signal graph Press the “Autoscale” button to display the whole content.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start Fig 19. SW_ADC_1_r02: “Acquisition” page, code histogram graph Press the “Autoscale” button to display the whole content. The table shows the range of output codes. 3.3.7 Info page This page will give practical information related to software and hardware settings: Fig 20. SW_ADC_1_r02: “Info” page QS_ADC1412D_10.doc Quick start © NXP B.V. 2010. All rights reserved. Rev.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start The information visible on this page are: • board serial number ; • HSDC software release number ; • HSDC-EXTMOD dll version ; • HSDC-EXTMOD vhdl version ; • HSDC-EXTMOD supply status ; • HSDC-EXTMOD clock capability and status version ; • HSDC-EXTMOD memory capability . QS_ADC1412D_10.doc Quick start © NXP B.V. 2010. All rights reserved. Rev.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 4. Appendix A.1: coherency calculation The coherency relies on the fact that clock and analog input signal are synchronized and the first and last samples being captured are adjoining samples: it ensures a continuous digitized time process for the FFT processing.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 5. Notes For any question, feel free to contact us at the following e-mail dataconvertersupport@nxp.com. QS_ADC1412D_10.doc Quick start © NXP B.V. 2010. All rights reserved. Rev.
NXP Semiconductors Quick start ADC1412D, ADC1212D, ADC1112D series Quick start 6. Contents 1. 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2. 2.1 2.2 3. 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.6.1 3.3.6.2 3.3.6.3 3.3.6.4 3.3.7 4. 5. 6. Overview of the ADC1412D, ADC1212D, ADC1112D demo board ......................................3 ADC1412D series ..............................................3 ADC1212D series ..............................................4 ADC1112D series ..................................
