Datasheet

ADC1010S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 28 December 2010 31 of 39
NXP Semiconductors
ADC1010S series
Single 10-bit ADC; CMOS or LVDS DDR digital outputs
Table 22. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - 0000 not used
3 INTREF_EN R/W programmable internal reference enable
0disable
1 active
2 to 0 INTREF[2:0] R/W programmable internal reference
000 FS = 2 V
001 FS = 1.78 V
010 FS = 1.59 V
011 FS = 1.42 V
100 FS = 1.26 V
101 FS = 1.12 V
110 FS = 1 V
111 reserved
Table 23. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - 000 not used
4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS
0CMOS
1 LVDS DDR
3 OUTBUF R/W output buffers enable
0output enabled
1 output disabled (high-Z)
2 OUTBUS_SWAP R/W output bus swapping
0 no swapping
1 output bus is swapping (MSB becomes LSB and vice
versa)
1 to 0 DATA_FORMAT[1:0] R/W output data format
00 offset binary
01 two’s complement
10 gray code
11 offset binary