Datasheet

ADC1010S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 28 December 2010 25 of 39
NXP Semiconductors
ADC1010S series
Single 10-bit ADC; CMOS or LVDS DDR digital outputs
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) can be used to capture the data delivered by the
ADC1010S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in
Figure 4
and Figure 5 respectively.
11.5.4 OuT-of-Range (OTR)
An out-of-range signal is provided on pin OTR. The latency of OTR is fourteen clock
cycles. The OTR response can be speeded up by enabling Fast OTR (bit
FASTOTR = logic 1; see Table 29
). In this mode, the latency of OTR is reduced to only
four clock cycles. The Fast OTR detection threshold (below full-scale) can be
programmed via bits FASTOTR_DET[2:0].
11.5.5 Digital offset
By default, the ADC1010S delivers output code that corresponds to the analog input.
However it is possible to add a digital offset to the output code via the SPI (bits
DIG_OFFSET[5:0]; see Table 25
).
11.5.6 Test patterns
For test purposes, the ADC1010S can be configured to transmit one of a number of
predefined test patterns (via bits TESTPAT_SEL[2:0]; see Table 26
). A custom test pattern
can be defined by the user (TESTPAT_USER[9:0]; see Table 27
and Table 28) and is
selected when TESTPAT_SEL[2:0] = 101. The selected test pattern is transmitted
regardless of the analog input.
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0] Resistor value (Ω)
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 60
Table 15. Fast OTR register
FASTOTR_DET[2:0] Detection level (dB)
000 −20.56
001 −16.12
010 −11.02
011 −7.82
100 −5.49
101 −3.66
110 −2.14
111 −0.86