Datasheet

ADC1010S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 28 December 2010 24 of 39
NXP Semiconductors
ADC1010S series
Single 10-bit ADC; CMOS or LVDS DDR digital outputs
The output resistance is 50 Ω and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both data and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 30
):
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see Table 23
).
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 30
) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and
Table 32
).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATA[1:0]; see Table 31
) in order to adjust the output logic
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
VDDO
3.5 mA
typ
D
x
P/D
x + 1
P
D
x
M/D
x + 1
M
OGND
100 Ω
−
005aaa05
8
+
−
+
RECEIVER
VDDO
OGND
005aaa05
9
D
x
P/D
x + 1
P
D
x
M/D
x + 1
M
100 Ω
3.5 mA
typ
+
−
+
−
RECEIVER