Datasheet

ADC1010S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 28 December 2010 22 of 39
NXP Semiconductors
ADC1010S series
Single 10-bit ADC; CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode
voltage of the differential input stage is set via internal 5 kΩ resistors.
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 27. Differential clock input
Sine
clock input
CLKP
CLKM
005aaa17
3
Sine
clock input
CLKP
CLKM
005aaa05
4
LVPECL
clock input
005aaa17
2
CLKP
CLKM
V
cm(clk)
= common-mode voltage of the differential input stage.
Fig 28. Equivalent input circuit
CLKP
CLKM
005aaa05
6
Package ESD Parasitics
5 kΩ 5 kΩ
V
cm(clk)
SE_SEL SE_SEL