Datasheet

ADC1010S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 28 December 2010 2 of 39
NXP Semiconductors
ADC1010S series
Single 10-bit ADC; CMOS or LVDS DDR digital outputs
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number f
s
(Msps) Package
Name Description Version
ADC1010S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 × 6 × 0.85 mm
SOT618-1
ADC1010S105HN/C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 × 6 × 0.85 mm
SOT618-1
ADC1010S080HN/C1 80 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 × 6 × 0.85 mm
SOT618-1
ADC1010S065HN/C1 65 HVQFN40 plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; body 6 × 6 × 0.85 mm
SOT618-1
Fig 1. Block diagram
ADC1010S
SPI INTERFACE
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
10-BIT
PIPELINED
T/H
INPUT
STAGE
INP
OTR
CS
SDIO/ODS
SCLK/DFS
PWD
REFT
CMOS:
D9 to D0
or
LVDS DDR:
D8_D9_M to D0_D1_M
D8_D9_P to D0_D1_P
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
REFB
CLKMCLKP
SENSE
VREF
VCM
005aaa134
OE
CMOS:
DAV
or
LVDS DDR:
DAVP
DAVM