Datasheet

ADC1010S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 2 — 28 December 2010 19 of 39
NXP Semiconductors
ADC1010S series
Single 10-bit ADC; CMOS or LVDS DDR digital outputs
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 12
.
[1] The voltage on pin VREF is doubled internally to generate the internal reference voltage.
Figure 21 to Figure 24 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
Fig 20. Reference equivalent schematic
Table 12. Reference selection
Selection SPI bit
INTREF_EN
SENSE pin VREF pin Full-scale (p-p)
internal
(Figure 21
)
0 AGND 330 pF capacitor to AGND 2 V
internal
(Figure 22
)
0 pin VREF connected to pin SENSE and via
a 330 pF capacitor to AGND
1 V
external
(Figure 23
)
0V
DDA
external voltage between
0.5 V and 1 V
[1]
1 V to 2 V
internal via SPI
(Figure 24
)
1 pin VREF connected to pin SENSE and via
330 pF capacitor to AGND
1 V to 2 V
EXT_ref
EXT_ref
005aaa164
REFT
REFB
SENSE
VREF
SELECTION
LOGIC
BANDGAP
REFERENCE
ADC CORE
BUFFER
REFERENCE
AMP