Datasheet

74LVC161 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 30 September 2013 5 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, one and two;
inhibit.
Fig 7. Timing sequence
mna909
CP
PE
TC
MR
inhibitcount
CEP
CET
D0
D2
D1
D3
Q0
Q2
Q1
Q3
reset preset
12 13 14 15 0 1 2