Datasheet

74LVC161 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 30 September 2013 13 of 22
NXP Semiconductors
74LVC161
Presettable synchronous 4-bit binary counter; asynchronous reset
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 12. Set-up and hold times for the input (Dn) and parallel enable input (PE)
mna914
GND
GND
GND
t
h
t
h
t
su
t
su
t
su
t
h
t
h
t
su
V
M
V
M
V
M
V
I
V
I
CP input
PE input
Dn input
V
I
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 13. CEP and CET set-up and hold times
mna915
t
h
t
su
t
h
t
su
GND
V
I
V
M
V
M
GND
V
I
CP input
CEP, CET input
Table 8. Measurement points
Supply voltage Input Output
V
CC
V
I
V
M
V
M
1.2 V V
CC
0.5  V
CC
0.5  V
CC
1.65 V to 1.95 V V
CC
0.5  V
CC
0.5  V
CC
2.3 V to 2.7 V V
CC
0.5  V
CC
0.5  V
CC
2.7 V 2.7 V 1.5 V 1.5 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V