Datasheet

1. General description
The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device
and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has
a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common
input/output (nZ). All three switches share an enable input (E
). A HIGH on E causes all
switches into the high-impedance OFF-state, independent of Sn.
V
CC
and GND are the supply voltage connections for the digital control inputs (Sn and E).
The V
CC
to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between V
CC
as a positive limit and V
EE
as a negative limit. V
CC
 V
EE
may not
exceed 6 V. For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND
(typically ground). V
EE
and V
SS
are the supply voltage connections for the switches.
2. Features and benefits
 Optimized for low-voltage applications: 1.0 V to 3.6 V
 Accepts TTL input levels between V
CC
= 2.7 V and V
CC
= 3.6 V
 Low ON resistance:
 180  (typical) at V
CC
 V
EE
= 2.0 V
 100  (typical) at V
CC
 V
EE
= 3.0 V
 75  (typical) at V
CC
 V
EE
= 4.5 V
 Logic level translation:
 To enable 3 V logic to communicate with 3 V analog signals
 Typical ‘break before make’ built in
 ESD protection:
 HBM JESD22-A114-C exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V
 Multiple package options
 Specified from 40 Cto+85C and from 40 Cto+125C
74LV4053
Triple single-pole double-throw analog switch
Rev. 5 — 18 September 2014 Product data sheet