Datasheet

74HC73_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 19 March 2008 9 of 16
NXP Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
Table 8. Measurement points
Type Input Output
V
I
V
M
V
M
74HC73 V
CC
0.5V
CC
0.5V
CC
Test data is given in Table 9.
Definitions for test circuit:
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
C
L
= Load capacitance including jig and probe capacitance.
Fig 8. Test circuit for measuring switching times
001aah768
t
W
t
W
t
r
t
r
t
f
V
M
V
I
negative
pulse
GND
V
I
positive
pulse
GND
10 %
90 %
90 %
10 %
V
M
V
M
V
M
t
f
V
CC
DUT
R
T
V
I
V
O
C
L
G
Table 9. Test data
Type Input Load
V
I
t
r
, t
f
C
L
74HC73 V
CC
6 ns 15 pF, 50 pF