Datasheet

74HC73_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 19 March 2008 7 of 16
NXP Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
[1] t
pd
is the same as t
PHL
, t
PLH
.
[2] t
t
is the same as t
THL
, t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+∑(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
∑(C
L
× V
CC
2
× f
o
) = sum of outputs.
t
h
hold time nJ, nK to nCP; see Figure 6
V
CC
= 2.0 V 3 −8- 3 3 - ns
V
CC
= 4.5 V 3 −3- 3 - 3 - ns
V
CC
= 6.0 V 3 −2- 3 - 3 ns
f
max
maximum
frequency
nCP input; see Figure 6
V
CC
= 2.0 V 6.0 23 - 4.8 4.0 - MHz
V
CC
= 4.5 V 30 70 - 24 - 20 - MHz
V
CC
= 6.0 V 35 83 - 28 - 24 - MHz
V
CC
= 5.0 V; C
L
= 15 pF - 77 - - - MHz
C
PD
power
dissipation
capacitance
per flip-flop;
V
I
= GND to V
CC
[3]
-30- - - - - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max