Datasheet

74HC73_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 19 March 2008 6 of 16
NXP Semiconductors
74HC73
Dual JK flip-flop with reset; negative-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 8
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
t
pd
propagation
delay
nCP to nQ; see Figure 6
[1]
V
CC
= 2.0 V - 52 160 - 200 - 240 ns
V
CC
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
= 6.0 V - 15 27 - 34 - 41 ns
V
CC
= 5.0 V; C
L
= 15 pF - 16 - - - - - ns
n
CP to nQ; see Figure 6
V
CC
= 2.0 V - 52 160 - 200 - 240 ns
V
CC
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
= 6.0 V - 15 27 34 - 41 ns
V
CC
= 5.0 V; C
L
= 15 pF - 16 - - ns
n
R to nQ, nQ; see Figure 7
V
CC
= 2.0 V - 50 145 - 180 - 220 ns
V
CC
= 4.5 V - 18 29 - 36 - 44 ns
V
CC
= 6.0 V - 14 25 31 - 38 ns
V
CC
= 5.0 V; C
L
= 15 pF - 15 - - - - - ns
t
t
transition time nQ, nQ; see Figure 6
[2]
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
V
CC
= 6.0 V - 6 13 16 - 19 ns
t
W
pulse width nCP input, HIGH or LOW;
see
Figure 6
V
CC
= 2.0 V 80 22 - 100 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 ns
n
R input, HIGH or LOW;
see
Figure 7
V
CC
= 2.0 V 80 22 - 100 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 ns
t
rec
recovery time nR to nCP; see Figure 7
V
CC
= 2.0 V 80 22 - 100 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 ns
t
su
set-up time nJ, nK to nCP; see Figure 6
V
CC
= 2.0 V 80 22 - 100 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 ns