Datasheet

74HC_HCT597 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 15 April 2014 5 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
6. Functional description
[1] H = HIGH voltage level.
L = LOW voltage level.
X = don’t care.
 = positive-going transition.
Table 3. Function table
[1]
Inputs Function
STCP SHCP PL MR
 X X X data loaded to input latches
 X L H data loaded from inputs to shift register
no clock edge X L H data transferred from input flip-flops to shift register
X X L L invalid logic, state of shift register is indeterminate
when signals removed
X X H L shift register cleared
X  H H shift register clocked Qn = Qn1, Q0 = DS
Fig 7. Timing diagram
DDD
6+&3
67&3
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// / ////////++++ ++ +
+
'
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4
UHVHW
VKLIW
UHJLVWHU
ORDGLQSXW
UHJLVWHU
SDUDOOHOORDG
VKLIWUHJLVWHU
ORDGLQSXW
UHJLVWHU
05
SDUDOOHOORDG
VKLIWUHJLVWHU
SDUDOOHOORDGERWK
LQSXWDQGVKLIWUHJLVWHUV
VHULDOVKLIW
VHULDOVKLIW VHULDOVKLIWVHULDOVKLIW
3/