Datasheet
74HC_HCT597 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 15 April 2014 4 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration DIP16 and SO16 Fig 6. Pin configuration SSOP16 and TSSOP16
+&
+&7
'
9
&
&
'
'
'
'
6
'
3
/
'
67&3
'
6+&3
'
0
5
*1'
4
DDD
+&
+&7
'
9
&
&
'
'
'
'
6
'
3
/
'
67&3
'
6+&3
'
0
5
*1'
4
DDD
Table 2. Pin description
Symbol Pin Description
GND 8 ground (0 V)
Q 9 serial data output
MR
10 asynchronous master reset input (active LOW)
SHCP 11 shift register clock input (LOW-to-HIGH, edge-triggered)
STCP 12 storage register clock input (LOW-to-HIGH, edge-triggered)
PL
13 parallel load input (active LOW)
DS 14 serial data input
D0, D1, D2, D3,
D4, D5, D6, D7
15, 1, 2, 3, 4, 5, 6, 7 parallel data inputs
V
CC
16 supply voltage