Datasheet

74HC_HCT597 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 15 April 2014 12 of 23
NXP Semiconductors
74HC597; 74HCT597
8-bit shift register with input flip-flops
[1] t
pd
is the same as t
PLH
and t
PHL
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
 V
CC
2
 f
i
 N+(C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
 V
CC
2
 f
o
) = sum of outputs.
11. Waveforms
t
h
hold time Dn to STCP; see
Figure 12
V
CC
= 4.5 V 5 1- 5 - 5 - ns
PL
, DS to SHCP; see
Figure 12
V
CC
= 4.5 V 5 2- 5 - 5 - ns
f
max
maximum
frequency
SHCP; see Figure 8
V
CC
= 4.5 V 30 75 - 24 - 20 - MHz
V
CC
= 5.0 V; C
L
= 15 pF - 83 - - - - - MHz
C
PD
power
dissipation
capacitance
C
L
= 50 pF; f = 1 MHz;
V
I
=GND toV
CC
 1.5 V
[3]
-32- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 14.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. Shift clock and storage clock inputs to output, propagation delays, pulse widths and maximum clock
frequency
I
PD[
W
:
W
3+/
W
3/+
9
,
*1'
9
2+
9
2/
4RXWSXW
67&36+&3
LQSXW
9
0
9
0
DDD