Datasheet

74HC_HCT4052_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 22 November 2012 4 of 26
NXP Semiconductors
74HC4052-Q100; 74HCT4052-Q100
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 5. Pin configuration for SO16 and TSSOP16 Fig 6. Pin configuration for DHVQFN16
74HC4052-Q100
74HCT4052-Q100
2Y0 V
CC
2Y2 1Y2
2Z 1Y1
2Y3 1Z
2Y1 1Y0
E 1Y3
V
EE
S0
GND S1
aaa-003162
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
aaa-003163
74HC4052-Q100
74HCT4052-Q100
V
EE
V
CC
(1)
S0
E 1Y3
2Y1 1Y0
2Y3 1Z
2Z 1Y1
2Y2 1Y2
GND
S1
2Y0 V
CC
Transparent top view
7 10
6 11
5 12
4
13
3 14
2 15
8 9
1
16
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
2Y0, 2Y1, 2Y2, 2Y3 1, 5, 2, 4 independent input or output
1Z, 2Z 13, 3 common input or output
E
6 enable input (active LOW)
V
EE
7 negative supply voltage
GND 8 ground (0 V)
S0, S1 10, 9 select logic input
1Y0, 1Y1, 1Y2, 1Y3 12, 14, 15, 11 independent input or output
V
CC
16 positive supply voltage