Datasheet

74HC4024 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 31 October 2013 3 of 19
NXP Semiconductors
74HC4024
7-stage binary ripple counter
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH clock transition;
= HIGH-to-LOW clock transition.
Fig 5. Pin configuration
74HC4024
CP V
CC
MR n.c.
Q6 Q0
Q5 Q1
Q4 n.c.
Q3 Q2
GND n.c.
001aab905
1
2
3
4
5
6
7 8
10
9
12
11
14
13
Table 2. Pin description
Symbol Pin Description
CP
1 clock input (HIGH-to-LOW, edge-triggered)
MR 2 master reset input (active HIGH)
Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0 3, 4, 5, 6, 9, 11, 12 parallel output
GND 7 ground (0 V)
n.c. 8, 10, 13 not connected
V
CC
14 positive supply voltage
Table 3. Function table
[1]
Input Output
MR CP Qn
HXL
L no change
count