Datasheet

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 5 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration (SO20 and (T)SSOP20) Fig 6. Pin configuration (DIP20)
74HC299
74HCT299
S0 V
CC
OE1 S1
OE2 DSL
I/O6 Q7
I/O4 I/O7
I/O2 I/O5
I/O0 I/O3
Q0 I/O1
MR CP
GND DSR
001aai511
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
74HC299
74HCT299
S0 V
CC
OE1 S1
OE2 DSL
I/O6 Q7
I/O4 I/O7
I/O2 I/O5
I/O0 I/O3
Q0 I/O1
MR CP
GND DSR
001aai457
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 2. Pin description
Symbol Pin Description
S0 1 mode select input
OE1 2 3-state output enable input (active LOW)
OE2 3 3-state output enable input (active LOW)
I/O6 4 parallel data input or 3-state parallel output (bus driver)
I/O4 5 parallel data input or 3-state parallel output (bus driver)
I/O2 6 parallel data input or 3-state parallel output (bus driver)
I/O0 7 parallel data input or 3-state parallel output (bus driver)
Q0 8 serial output (standard output)
MR 9 asynchronous master reset input (active LOW)
GND 10 ground (0 V)
DSR 11 serial data shift-right input
CP 12 clock input (LOW to HIGH, edge-triggered)
I/O1 13 parallel data input or 3-state parallel output (bus driver)
I/O3 14 parallel data input or 3-state parallel output (bus driver)
I/O5 15 parallel data input or 3-state parallel output (bus driver)
I/O7 16 parallel data input or 3-state parallel output (bus driver)
Q7 17 serial output (standard output)