Datasheet

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 15 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the
master reset to clock pulse removal time
001aai463
I/On, Q0, Q7
outputs
V
M
t
PHL
V
M
MR input
V
M
GND
GND
V
I
t
W
t
rec
CP input
V
OL
V
I
V
OH
Measurement points are given in Table 8.
Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse
001aai464
I/On, DSR, DSL, Sn
inputs
CP input
t
su
t
h
V
M
V
I
GND
GND
V
I
V
M
t
su
t
h