Datasheet

74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 14 of 24
NXP Semiconductors
74HC299; 74HCT299
8-bit universal shift register; 3-state
[6] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
= C
PD
× V
CC
2
× f
i
× N + Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
Σ(C
L
× V
CC
2
× f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching.
11. Waveforms
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL to
clock pulse set-up and hold times, the output transition times and the maximum clock frequency
001aai462
t
h
t
su
t
h
t
PHL
t
THL
t
TLH
t
W
t
PLH
t
su
1/f
max
V
M
V
M
V
M
CP input
V
I
GND
V
I
GND
V
OH
V
OL
I/On, DSR, DSL
inputs
I/On, Q0, Q7
outputs