Datasheet

74HC_HCT20 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 3 September 2012 3 of 16
NXP Semiconductors
74HC20; 74HCT20
Dual 4-input NAND gate
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: P
tot
derates linearly with 12 mW/K above 70 C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
Table 2. Pin description
Symbol Pin Description
1A, 1B, 1C, 1D 1, 2, 4, 5 data input
n.c. 3, 11 not connected
1Y 6 data output
GND 7 ground (0 V)
2Y 8 data output
2A, 2B, 2C, 2D 9, 10, 12, 13 data input
V
CC
14 supply voltage
Table 3. Function table
[1]
Input Output
nA nB nC nD nY
LXXXH
XLXXH
XXLXH
XXXLH
HHHHL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V
[1]
- 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V
[1]
- 20 mA
I
O
output current 0.5 V < V
O
< V
CC
+0.5V - 25 mA
I
CC
supply current - 50 mA
I
GND
ground current 50 - mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation
[2]
DIP14 package - 750 mW
SO14, and (T)SSOP14
packages
- 500 mW