Datasheet

74HC_HCT20 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 3 — 3 September 2012 2 of 16
NXP Semiconductors
74HC20; 74HCT20
Dual 4-input NAND gate
4. Functional diagram
5. Pinning information
5.1 Pinning
Fig 1. Functional diagram Fig 2. Logic symbol
$
%
&
'




<

$
%
&
'




<

DDD
$
%
&
'




<

$
%
&
'




<

DDD
Fig 3. IEC Logic symbol Fig 4. Logic diagram












DDD
$
%
&
'
<
DDD
Fig 5. Pin configuration SOT27-1 and SOT108-1 Fig 6. Pin configuration SOT337-1 and SOT402-1
9
&&
'
&
QF
%
$
<






 






+&
+&7
DDD

$

%
Q
F

&

'

<
*1
'

$
9
&&

%
'
Q
F
&

&
QF

'
%

<
$
*1
'
<














+&
+&7
DDD