Datasheet

Product data sheet Rev. 03 — 14 March 2008 4 of 22

NXP Semiconductors

74HC165; 74HCT165

8-bit parallel-in/serial out shift register

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level;

l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

q = state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition;

X = don’t care;

↑ = LOW-to-HIGH clock transition.

Table 2. Pin description

Symbol Pin Description

PL 1 asynchronous parallel load input (active LOW)

CP 2 clock input (LOW-to-HIGH edge-triggered)

Q7 7 complementary output from the last stage

GND 8 ground (0 V)

Q7 9 serial output from the last stage

DS 10 serial data input

D0 to D7 11, 12, 13, 14, 3, 4, 5, 6 parallel data inputs (also referred to as Dn)

CE 15 clock enable input (active LOW)

16 positive supply voltage

Table 3. Function table

[1]

Operating modes Inputs Qn registers Outputs

PL CE CP DS D0 to D7 Q0 Q1 to Q6 Q7 Q7

parallel load L XXXLLL to LLH

LXXXHHH to HHL

serial shift H L ↑ l X L q0 to q5 q6

HL ↑ h X H q0 to q5 q6

H ↑ L l X L q0 to q5 q6

H ↑ L h X H q0 to q5 q6

hold “do nothing” H H X X X q0 q1 to q6 q7

H X H X X q0 q1 to q6 q7