Datasheet

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 14 March 2008 12 of 22
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 8. The parallel load (PL) pulse width, the parallel load to output (Q7 or Q7) propagation delays, the parallel
load to clock (CP) and clock enable (
CE) recovery time
mna988
PL input
CE, CP input
Q7 or Q7 output
t
PHL
t
W
t
rec
V
M
V
OH
V
I
GND
V
I
GND
V
OL
V
M
V
M
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 9. The data input (D7) to output (Q7 or Q7) propagation delays when PL is LOW
mna989
D7 input
Q7 output
Q7 output
t
PHL
t
PHL
V
M
V
OH
V
I
GND
V
OH
V
OL
V
OL
V
M
t
PLH
t
PLH
V
M