Datasheet

74HC_HCT165_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 14 March 2008 11 of 22
NXP Semiconductors
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
= C
PD
× V
CC
2
× f
i
+ Σ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
Σ (C
L
× V
CC
2
× f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V.
12. Waveforms
C
PD
power
dissipation
capacitance
per package;
V
I
= GND to V
CC
− 1.5 V
[3]
-35- - - - - pF
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 12
Symbol Parameter Conditions 25 °C −40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
mna987
CP or CE input
Q7 or Q7 output
t
PHL
t
THL
t
TLH
t
PLH
t
W
1/f
max
V
M
V
OH
V
I
GND
V
OL
V
M