Datasheet
74HC_HCT163 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 2 June 2014 14 of 24
NXP Semiconductors
74HC163; 74HCT163
Presettable synchronous 4-bit binary counter; synchronous reset
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8
.
Fig 13. The master reset (MR) set-up and hold times
&3
LQSXW
*1'
9
,
DDD
05LQSXW
*1'
9
,
9
0
9
0
W
K
W
K
W
VX
W
VX
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8
.
Fig 14. The count enable input (CEP) and count enable carry input (CET) set-up and hold times
&3
LQSXW
*1'
9
,
DDD
&(3
&(7
LQSXW
*1'
9
,
9
0
9
0
W
K
W
K
W
VX
W
VX
Table 8. Measurement points
Type Input Output
V
M
V
I
V
M
74HC163 0.5 V
CC
GND to V
CC
0.5 V
CC
74HCT163 1.3 V GND to 3 V 1.3 V