Datasheet
74HC_HCT163 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 2 June 2014 13 of 24
NXP Semiconductors
74HC163; 74HCT163
Presettable synchronous 4-bit binary counter; synchronous reset
Measurement points are given in Table 8.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 11. The count enable carry input (CET) to terminal count output (TC) propagation delays and output
transition times
DDD
&(7LQSXW
7&RXWSXW
W
3/+
W
3+/
9
0
9
0
9
2/
9
2+
*1'
9
,
W
7/+
W
7+/
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8
.
Fig 12. The data input (Dn) and parallel enable input (PE) set-up and hold times
DDD
3(LQSXW
*1'
9
,
*1'
9
,
&3
LQSXW
9
0
W
VX
W
K
9
0
'QLQSXW
*1'
9
,
9
0
W
VX
W
K
W
VX
W
K
W
VX
W
K