Datasheet

74HC_HCT163 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 2 June 2014 12 of 24
NXP Semiconductors
74HC163; 74HCT163
Presettable synchronous 4-bit binary counter; synchronous reset
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
 V
CC
2
 f
i
 N+(C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
 V
CC
2
 f
o
) = sum of outputs.
11. Waveforms
C
PD
power
dissipation
capacitance
V
I
= GND to V
CC
 1.5 V;
V
CC
=5V; f
i
=1MHz
[3]
-35- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit see Figure 15.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
Logic levels V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 10. The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum
frequency
DDD
&3
LQSXW
9
,
*1'
9
2+
9
2/
4Q
7&
RXWSXW
W
3+/
W
3/+
W
:
9
0
9
0
I
PD[
W
7+/
W
7/+
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