User Manual

© NXP Laboratories UK 2012 JN-DS-JN5148-001-Myy 1v5 7
4. Pin Configurations
1
2
3
4
16
ADC4
DAC1
DAC2
COMP2+
COMP2-
SPICLK
SPIMISO
SPIMOSI
SPISSZ
DIO0
DIO1
DIO2
SPISSM
SPISWP
DIO3
DIO4 DIO5 DIO6 DIO7 DIO8 DIO9
DIO10
DIO11
VDD
GND
VSSA
ADC3
ADC2
ADC1
DIO20
DIO19
DIO18
DIO17
DIO16
DIO15
RESETN
DIO14
DIO13
DIO12
5
6
7
8
9
10
11
12
13
14
15
17 18 19 20 21 22 23 24 25 26
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
COMP1+
COMP1-
43
NC
VREF
42
Figure 1: Pin Configuration (top view)
Note that the same basic pin configuration applies for all module designs. However, DIO3 (pin 15) and DIO2 (pin 12)
are not available on the high power modules (M06) and, the pins NC (pin 42) and VREF (pin 43) are not available on
the standard modules (M00 and M03).