User Manual

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Table Of Contents

1 Introduction
- 1.1 Wireless Transceiver
- 1.2 RISC CPU and Memory
- 1.3 Peripherals
- 1.4 Block Diagram
2 Pin Configurations
- 2.1 Pin Assignment
- 2.2 Pin Descriptions
3 CPU
4 Memory Organisation
- 4.1 ROM
- 4.2 RAM
- 4.3 OTP eFuse Memory
- 4.4 External Memory
  - 4.4.1 External Memory Encryption
- 4.5 Peripherals
- 4.6 Unused Memory Addresses
5 System Clocks
- 5.1 16MHz System Clock
  - 5.1.1 32MHz Oscillator
  - 5.1.2 24MHz RC Oscillator
- 5.2 32kHz System Clock
6 Reset
- 6.1 Internal Power-on Reset
- 6.2 External Reset
- 6.3 Software Reset
- 6.4 Brown-out Detect
- 6.5 Watchdog Timer
7 Interrupt System
- 7.1 System Calls
- 7.2 Processor Exceptions
- 7.3 Hardware Interrupts
8 Wireless Transceiver
- 8.1 Radio
  - 8.1.1 Radio External Components
  - 8.1.2 Antenna Diversity
- 8.2 Modem
- 8.3 Baseband Processor
- 8.4 Security Coprocessor
- 8.5 Location Awareness
- 8.6 Higher Data Rates
9 Digital Input/Output
10 Serial Peripheral Interface
11 Timers
- 11.1 Peripheral Timer/Counters
- 11.2 Tick Timer
- 11.3 Wakeup Timers
  - 11.3.1 RC Oscillator Calibration
12 Pulse Counters
13 Serial Communications
- 13.1 Interrupts
- 13.2 UART Application
14 JTAG Debug Interface
15 Two-Wire Serial Interface
- 15.1 Connecting Devices
- 15.2 Clock Stretching
- 15.3 Master Two-wire Serial Interface
- 15.4 Slave Two-wire Serial Interface
16 Four-Wire Digital Audio Interface
17 Random Number Generator
18 Sample FIFO
19 Intelligent Peripheral Interface
- 19.1 Data Transfer Format
- 19.2 JN5148 (Slave) Initiated Data Transfer
- 19.3 Remote (Master) Processor Initiated Data Transfer
20 Analogue Peripherals
- 20.1 Analogue to Digital Converter
- 20.2 Digital to Analogue Converter
  - 20.2.1 Operation
- 20.3 Comparators
21 Power Management and Sleep Modes
- 21.1 Operating Modes
  - 21.1.1 Power Domains
- 21.2 Active Processing Mode
  - 21.2.1 CPU Doze
- 21.3 Sleep Mode
- 21.4 Deep Sleep Mode
22 Electrical Characteristics
- 22.1 Maximum Ratings
- 22.2 DC Electrical Characteristics
- 22.3 AC Characteristics
Appendix A Mechanical and Ordering Information
- A.1 56-pin QFN Package Drawing
- A.2 PCB Decal
- A.3 Ordering Information
- A.4 Device Package Marking
- A.5 Tape and Reel Information
Appendix B Development Support
- B.1 Crystal Oscillators
- B.2 32MHz Oscillator
- B.3 32kHz Oscillator
- B.4 JN5148 Module Reference Designs
  - B.4.1 Schematic Diagram
  - B.4.2 PCB Design and Reflow Profile
- Related Documents
- RoHS Compliance
- Status Information
- Disclaimers
- Version Control
- Contact Details

Jennic

92 JN-DS-JN5148-001 1v2 © Jennic 2009

Preliminary

B.4 JN5148 Module Reference Designs

For customers wishing to integrate the JN5148 device directly into their system, Jennic provide a range of Module

Reference Designs, covering standard and high-power modules fitted with different Antennae

To ensure the correct performance, it is strongly recommended that where possible the design details provided by the

reference designs, are used in their exact form for all end designs, this includes component values, pad dimensions,

track layouts etc. In order to minimise all risks, it is recommended that the entire layout of the appropriate reference

module, if possible, be replicated in the end design.

For full detail please consult the Standard Module Reference Design JN-RD-6001

[7] , available to download from the

Jennic Support web site

(www.jennic.com/support)

B.4.1 Schematic Diagram

A schematic diagram of the JN5148 PCB antenna reference module is shown in Figure 55. Details of component

values and PCB layout constraints can be found in

Table 8.

Figure 55: JN5148 Printed Antenna Reference Module Schematic Diagram