User Manual

Jennic
8 JN-DS-JN5148-001 1v2 © Jennic 2009
Preliminary
1.4 Block Diagram
32-bit RISC CPU
Reset
SPI
Master
MUX
UART0
UART1
Wakeup
Timer1
Wakeup
Tim er0
Security
Coprocessor
DIO6/TXD0/JTAG_TDO
DIO7/RXD0/JTAG_T DI
DIO4/CTS0/JTAG_T CK
DIO5/RTS0/JTAG_T MS
DIO19/TXD1/JTAG_TDO
DIO1 7/CT S1/ IP_ SEL /DAI _S CK /
JTAG_TCK
DIO18/RT S1/IP_INT/DAI_SDOUT/
JTAG_TMS
Digital
Baseband
Radio
Programmable
Interrupt
Controller
Timer0
2-wire
Interface
Timer1
SPICLK
DI O1 0/T IM0OUT /32 KXT ALOUT
SPIMOSI
SPIMISO
SPISEL0
DIO0 /S PISE L1
DIO3 /S PISE L4/ RFTX
DIO2 /S PISE L3/ RFRX
DIO1 /S PISE L2/P C0
DIO9/T IM0CAP/32KXTALIN/32KIN
DIO8/T IM0CK_GT/PC1
D I O1 3 /T I M1 OU T /A D E/ D A I_ S D IN
DIO11/TIM1CK_GT/TIM2OUT
DIO12/TIM1CAP/ADO/DAI_WS
DIO14/SIF_CLK/IP_CLK
DIO15/SIF_D/IP_DO
DIO16/RXD1/IP_DI/JTAG_TDI
Fro m Perip herals
RE SET N
Wireless
Transceiver
32MHz Clock
Generator
XT A L_ IN
XT A L_OUT
RF_IN
VCOTUNE
Tick Tim er
Voltage
Regulators
1.8V
VDD1
VDD2
Intelligent
Peripheral
IBAIS
VB_XX
Cl ock Di vi der
Multiplier
Timer2
SPISEL1
SPISEL2
SPISEL3
SPISEL4
TXD0
RXD0
RTS0
CTS0
TXD1
RXD1
RTS1
CTS1
TIM0CK_GT
TIM0CAP
TIM0OUT
TIM1CK_GT
TIM1CAP
TIM1OUT
TIM2OUT
SIF_D
SIF_CLK
IP_DO
IP_DI
IP_INT
IP_CLK
IP_SEL
4-wire
Digital
Audio
Interface
I2S_OUT
I2S_DIN
I2S_CLK
I2S_SYNC
Pulse
Counters
PC0
PC1
JTAG
Debug
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_TDO
RAM
128kB
ROM
128kB
OTP
eFuse
32kHz
RC
Os c
32kHz Clock
Select
32KIN
32kHz
Clock
Gen
32KXTALIN
32KXTALOUT
Antenna
Diversity
ADO
ADE
Time
Of
Flight
Sample
FIFO
DIO20/RXD1/JTAG_TDI
24MHz
RC Osc
Comparator2
COMP2P
COMP2M
Comparator1
COMP1P/
EXT_PA_C
COMP1M/
EXT_PA_B
DAC1
DAC2
DAC1
DAC2
ADC
M
U
X
ADC4
ADC1
ADC2
ADC3
Temperature
Sensor
Supply Monitor
CPU and 16MHz
System Clock
Watch dog
Timer
Brown-out
Detect
Figure 1: JN5148 Block Diagram