User Manual

Jennic
46 JN-DS-JN5148-001 1v2 © Jennic 2009
Preliminary
15 Two-Wire Serial Interface
The JN5148 includes industry standard two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave
(SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a serial data
line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the following
features:
Common to both master and slave:
• Compatible with both I
2
C and SMbus peripherals
• Support for 7 and 10-bit addressing modes
• Optional pulse suppression on signal inputs
Master only:
• Multi-master operation
• Software programmable clock frequency
• Clock stretching and wait state generation
• Software programmable acknowledge bit
• Interrupt or bit-polling driven byte-by-byte data-transfers
• Bus busy detection
Slave only:
• Programmable slave address
• Simple byte level transfer protocol
• Write data flow control with optional clock stretching or acknowledge mechanism
• Read data preloaded or provided as required
15.1 Connecting Devices
The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO15 and DIO14 respectively. The serial
interface function of these pins is selected when the interface is enabled. They are both bi-directional lines,
connected internally to the positive supply voltage via weak (45kΩ) programmable pull-up resistors. However, it is
recommended that external 4.7kΩ pull-ups be used for reliable operation at high bus speeds, as shown in
Figure 31.
When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-
drain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is
solely dependent on the bus capacitance limit of 400pF.
SIF_CL K
SIF_D
VDD
D1_OUT
D1_IN CLK1_IN
CLK1_OUT
D2_IN CLK2_IN
CLK2_OUT
DEVICE 1 DEVICE 2
R
P
R
P
Pu llup
Resistors
D2_OUT
JN5148
SIF
DIO14
DIO15
Figure 31: Connection Details