User Manual

ManualsBrandsNXP Laboratories UK ManualsAudio EquipmentIEEE 802.15.4 Wireless Microcontroller

Table Of Contents

1 Introduction
- 1.1 Wireless Transceiver
- 1.2 RISC CPU and Memory
- 1.3 Peripherals
- 1.4 Block Diagram
2 Pin Configurations
- 2.1 Pin Assignment
- 2.2 Pin Descriptions
3 CPU
4 Memory Organisation
- 4.1 ROM
- 4.2 RAM
- 4.3 OTP eFuse Memory
- 4.4 External Memory
  - 4.4.1 External Memory Encryption
- 4.5 Peripherals
- 4.6 Unused Memory Addresses
5 System Clocks
- 5.1 16MHz System Clock
  - 5.1.1 32MHz Oscillator
  - 5.1.2 24MHz RC Oscillator
- 5.2 32kHz System Clock
6 Reset
- 6.1 Internal Power-on Reset
- 6.2 External Reset
- 6.3 Software Reset
- 6.4 Brown-out Detect
- 6.5 Watchdog Timer
7 Interrupt System
- 7.1 System Calls
- 7.2 Processor Exceptions
- 7.3 Hardware Interrupts
8 Wireless Transceiver
- 8.1 Radio
  - 8.1.1 Radio External Components
  - 8.1.2 Antenna Diversity
- 8.2 Modem
- 8.3 Baseband Processor
- 8.4 Security Coprocessor
- 8.5 Location Awareness
- 8.6 Higher Data Rates
9 Digital Input/Output
10 Serial Peripheral Interface
11 Timers
- 11.1 Peripheral Timer/Counters
- 11.2 Tick Timer
- 11.3 Wakeup Timers
  - 11.3.1 RC Oscillator Calibration
12 Pulse Counters
13 Serial Communications
- 13.1 Interrupts
- 13.2 UART Application
14 JTAG Debug Interface
15 Two-Wire Serial Interface
- 15.1 Connecting Devices
- 15.2 Clock Stretching
- 15.3 Master Two-wire Serial Interface
- 15.4 Slave Two-wire Serial Interface
16 Four-Wire Digital Audio Interface
17 Random Number Generator
18 Sample FIFO
19 Intelligent Peripheral Interface
- 19.1 Data Transfer Format
- 19.2 JN5148 (Slave) Initiated Data Transfer
- 19.3 Remote (Master) Processor Initiated Data Transfer
20 Analogue Peripherals
- 20.1 Analogue to Digital Converter
- 20.2 Digital to Analogue Converter
  - 20.2.1 Operation
- 20.3 Comparators
21 Power Management and Sleep Modes
- 21.1 Operating Modes
  - 21.1.1 Power Domains
- 21.2 Active Processing Mode
  - 21.2.1 CPU Doze
- 21.3 Sleep Mode
- 21.4 Deep Sleep Mode
22 Electrical Characteristics
- 22.1 Maximum Ratings
- 22.2 DC Electrical Characteristics
- 22.3 AC Characteristics
Appendix A Mechanical and Ordering Information
- A.1 56-pin QFN Package Drawing
- A.2 PCB Decal
- A.3 Ordering Information
- A.4 Device Package Marking
- A.5 Tape and Reel Information
Appendix B Development Support
- B.1 Crystal Oscillators
- B.2 32MHz Oscillator
- B.3 32kHz Oscillator
- B.4 JN5148 Module Reference Designs
  - B.4.1 Schematic Diagram
  - B.4.2 PCB Design and Reflow Profile
- Related Documents
- RoHS Compliance
- Status Information
- Disclaimers
- Version Control
- Contact Details

Jennic

Preliminary

sent from a slave, it should perform transmit using dummy data. An interrupt can be generated when the transaction

has completed or alternatively the interface can be polled.

If a slave device wishes to signal the JN5148 indicating that it has data to provide, it may be connected to one of the

DIO pins that can be enabled as an interrupt.

Figure 21 shows a complex SPI transfer, reading data from a FLASH device, that can be achieved using the SPI

master interface. The slave select line must stay low for many separate SPI accesses, and therefore manual slave

select mode must be used. The required slave select can then be asserted (active low) at the start of the transfer. A

sequence 8 and 32 bit transfers can be used to issue the command and address to the FLASH device and then to

read data back. Finally, the slave select can be deselected to end the transaction.

1234567

Instruction (0x03)

23 22 21 3 2 1 0

8 9 10 28 29 30 31

24-bit Address

MSB

Instruction Transaction

7 6 5 4 3 2 1 0

MSB

1234

8N-1

3 2 1 0

LSB

Read Data Bytes Transaction(s) 1-N

SPISEL

SPICLK

SPIMOSI

SPIMISO

SPISEL

SPICLK

SPIMOSI

SPIMISO

8910

7 6 5

MSB

Byte 1 Byte 2 Byte N

value unused by peripherals

Figure 21: Example SPI Waveforms – Reading from FLASH device using Mode 0