User Manual

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Table Of Contents

1 Introduction
- 1.1 Wireless Transceiver
- 1.2 RISC CPU and Memory
- 1.3 Peripherals
- 1.4 Block Diagram
2 Pin Configurations
- 2.1 Pin Assignment
- 2.2 Pin Descriptions
3 CPU
4 Memory Organisation
- 4.1 ROM
- 4.2 RAM
- 4.3 OTP eFuse Memory
- 4.4 External Memory
  - 4.4.1 External Memory Encryption
- 4.5 Peripherals
- 4.6 Unused Memory Addresses
5 System Clocks
- 5.1 16MHz System Clock
  - 5.1.1 32MHz Oscillator
  - 5.1.2 24MHz RC Oscillator
- 5.2 32kHz System Clock
6 Reset
- 6.1 Internal Power-on Reset
- 6.2 External Reset
- 6.3 Software Reset
- 6.4 Brown-out Detect
- 6.5 Watchdog Timer
7 Interrupt System
- 7.1 System Calls
- 7.2 Processor Exceptions
- 7.3 Hardware Interrupts
8 Wireless Transceiver
- 8.1 Radio
  - 8.1.1 Radio External Components
  - 8.1.2 Antenna Diversity
- 8.2 Modem
- 8.3 Baseband Processor
- 8.4 Security Coprocessor
- 8.5 Location Awareness
- 8.6 Higher Data Rates
9 Digital Input/Output
10 Serial Peripheral Interface
11 Timers
- 11.1 Peripheral Timer/Counters
- 11.2 Tick Timer
- 11.3 Wakeup Timers
  - 11.3.1 RC Oscillator Calibration
12 Pulse Counters
13 Serial Communications
- 13.1 Interrupts
- 13.2 UART Application
14 JTAG Debug Interface
15 Two-Wire Serial Interface
- 15.1 Connecting Devices
- 15.2 Clock Stretching
- 15.3 Master Two-wire Serial Interface
- 15.4 Slave Two-wire Serial Interface
16 Four-Wire Digital Audio Interface
17 Random Number Generator
18 Sample FIFO
19 Intelligent Peripheral Interface
- 19.1 Data Transfer Format
- 19.2 JN5148 (Slave) Initiated Data Transfer
- 19.3 Remote (Master) Processor Initiated Data Transfer
20 Analogue Peripherals
- 20.1 Analogue to Digital Converter
- 20.2 Digital to Analogue Converter
  - 20.2.1 Operation
- 20.3 Comparators
21 Power Management and Sleep Modes
- 21.1 Operating Modes
  - 21.1.1 Power Domains
- 21.2 Active Processing Mode
  - 21.2.1 CPU Doze
- 21.3 Sleep Mode
- 21.4 Deep Sleep Mode
22 Electrical Characteristics
- 22.1 Maximum Ratings
- 22.2 DC Electrical Characteristics
- 22.3 AC Characteristics
Appendix A Mechanical and Ordering Information
- A.1 56-pin QFN Package Drawing
- A.2 PCB Decal
- A.3 Ordering Information
- A.4 Device Package Marking
- A.5 Tape and Reel Information
Appendix B Development Support
- B.1 Crystal Oscillators
- B.2 32MHz Oscillator
- B.3 32kHz Oscillator
- B.4 JN5148 Module Reference Designs
  - B.4.1 Schematic Diagram
  - B.4.2 PCB Design and Reflow Profile
- Related Documents
- RoHS Compliance
- Status Information
- Disclaimers
- Version Control
- Contact Details

Jennic

32 JN-DS-JN5148-001 1v2 © Jennic 2009

Preliminary

9 Digital Input/Output

There are 21 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a

selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the device,

see section 2.1. Once a peripheral is enabled it takes precedence over the device pins. Refer to the individual

module sections for a full description of the alternate peripherals functions. Following a reset (and whilst the reset

input is held low), all peripherals are off and the DIO pins are configured as inputs with the internals pull-ups turned

on.

When a peripheral is not enabled, the DIO pins associated with it can be used as digital inputs or outputs. Each pin

can be controlled individually by setting the direction and then reading or writing to the pin.

The individual pull-up resistors, R

, can also be enabled or disabled as needed and the setting is held through sleep

cycles. The pull-ups are generally configured once after reset depending on the external components and

functionality. For instance, outputs should generally have the pull-ups disabled. An input that is always driven should

also have the pull-up disabled.

When configured as an input each pin can be used to generate an interrupt upon a change of state (selectable

transition either from low to high or high to low); the interrupt can be enabled or disabled. When the device is

sleeping, these interrupts become events that can be used to wake the device up. Equally the status of the interrupt

may be read. See section

21 Power Management and Sleep Modes for further details on sleep and wakeup.

The state of all DIO pins can be read, irrespective of whether the DIO is configured as an input or an output.

Throughout a sleep cycle the direction of the DIO, and the state of the outputs, is held. This is based on the resultant

of the GPIO Data/ Direction registers and the effect of any enabled peripherals at the point of entering sleep.

Following a wake-up these directions and output values are maintained under control of the GPIO data / direction

registers. Any peripherals enabled before the sleep cycle are not automatically re-enabled, this must be done through

software after the wake-up.

For example, if DIO0 is configured to be SPISEL1 then it becomes an output. The output value is controlled by the

SPI functional block. If the device then enters a sleep cycle, the DIO will remain an output and hold the value being

output when entering sleep. After wake-up the DIO will still be an output with the same value but controlled from the

GPIO Data/Direction registers. It can be altered with the software functions that adjust the DIO, or the application may

re-configure it to be SPISEL1.

Unused DIO pins are recommended to be set as inputs with the pull-up enabled.