Data Sheet

90 JN-DS-JN5142 1v0 © NXP Laboratories UK 2012
1
40 39 38 37 36 35 34 33 32 31
VSSA
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
20
1918
1716
1514
131211
COMP1P
COMP1M
RESETN
XTAL_OUT
XTAL_IN
VB_SYNTH
VCOTUNE (NC)
VB_VCO
VDD1
IBIAS
VREF
VB_RF2
RF_IN
VB_RF
ADC1
SPISEL1 SPISEL2
DIO2 DIO3
SPICLK
VSS1
SPIMISO
SPIMOSI
SPISELO
VB_RAM
CTS0
RTS0
TXD0
RXD0
VDD2
SIF_D
VSS2
SIF_CLK
DIO13
DIO12
VB_DIG
DIO11
TIM0OUT
TIM0CAP TIM0CK_GT
C7: 100nF
2-wire Serial Port Timer0
C16: 100nF
UART0/JTAG
C6: 100nF
Serial
Flash
Memory
VDD
SDO
WP
VSS
SS VCC
HOLD
CLK
SDI
SPI Select
Analogue IO
C12: 47pF C3: 100nFC1: 47pF
L1: 5.6nH
L2: 2.7nH
VB_RF
R1: 43k
To coaxial socket
or integrated antenna
C20: 100nF
C14: 100nFC13: 10µF
VDD
C2: 10nF
C15: 100nF
C10: 15pF
C11: 15pF
Y1
Analogue IO
VDD
VB_RF1
Figure 54: JN5142 Printed Antenna Reference Module Schematic Diagram