Data Sheet

© NXP Laboratories UK 2012 JN-DS-JN5142 1v0 9
2 Pin Configurations
1
40 39 38 37 36 35 34 33 32 31
VSSA
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
20
1918
1716
1514
131211
DIO16/COMP1P/SIF_CLK
DIO17/COMP1M/SIF_D
RESETN
XTAL_OUT
XTAL_IN
VB_SYNTH
VCOTUNE
VB_VCO
VDD1
IBIAS
VREF/ADC2
VB_RF2
RF_IN
VB_RF1
ADC1
DIO0/SPISEL1/ADC3
DIO1/SPISEL2/PC0/ADC4
DIO2/RFRX/TIM0CK_GT
DIO3/RFTX/TIM0CAP
SPICLK
VSS1
SPIMISO
SPIMOSI
SPISELO
VB_RAM
DIO4/CTS0*/TIM0OUT
DIO5/RTS0*/PWM1/PC1
DIO6/TXD0*/PWM2
DIO7/RXD0*/PWM3
VDD2
DIO15/SIF_D/RXD0*/SPISEL2 VSS2 DIO14/SIF_CLK/TXD0*/SPISEL1 DIO13/ADE/PWM3/RTS0* DIO12/ADO/PWM2/CTS0* VB_DIG DIO11/PWM1 DIO10/TIM0OUT/32KXTALOUT DIO9/TIM0CAP/32KXTALIN/32KIN DIO8/TIM0CK_GT/PC1
*Note: JTAG occupies UART0 pins in either position
Figure 2: 40-pin QFN Configuration (top view)
 Note: Please refer to Appendix B.4 JN5142 Module Reference
Design for important applications information regarding the
connection of the PADDLE to the PCB.