Data Sheet

ManualsBrandsNXP Laboratories UK ManualsElectronicsJN5142-001-M03 IEEE802.15.4 Wireless Module

B.4 JN5142 Module Reference Designs

For customers wishing to integrate the JN5142 device directly into their system, NXP provide a range of Module

Reference Designs, covering standard and high-power modules fitted with different Antennae

To ensure the correct performance, it is strongly recommended that where possible the design details provided by the

reference designs, are used in their exact form for all end designs, this includes component values, pad dimensions,

track layouts etc. In order to minimise all risks, it is recommended that the entire layout of the appropriate reference

module, if possible, be replicated in the end design.

For full details, see [6]. Please contact technical support via the on-line tech-support system.

(www.jennic.com/support)

B.4.1 Schematic Diagram

A schematic diagram of the JN5142 PCB antenna reference module is shown in

40 39 38 37 36 35 34 33 32 31

VSSA

1918

1716

1514

131211

COMP1P

COMP1M

RESETN

XTAL_OUT

XTAL_IN

VB_SYNTH

VCOTUNE (NC)

VB_VCO

VDD1

IBIAS

VREF

VB_RF2

RF_IN

VB_RF

ADC1

SPISEL1

SPISEL2

DIO2

DIO3

SPICLK

VSS1

SPIMISO

SPIMOSI

SPISELO

VB_RAM

CTS0

RTS0

TXD0

RXD0

VDD2

SIF_D

VSS2

SIF_CLK

DIO13

DIO12

VB_DIG

DIO11

TIM0OUT

TIM0CAP

TIM0CK_GT

C7: 100nF

2-wire Serial Port Timer0

C16: 100nF

UART0/JTAG

C6: 100nF

Serial

Flash

Memory

VDD

SDO

VSS

SS VCC

HOLD

CLK

SDI

SPI Select

Analogue IO

C12: 47pF C3: 100nFC1: 47pF

L1: 5.6nH

L2: 2.7nH

VB_RF

R1: 43k

To coaxial socket

or integrated antenna

C20: 100nF

C14: 100nFC13: 10µF

VDD

C2: 10nF

C15: 100nF

C10: 15pF

C11: 15pF

Analogue IO

VDD

VB_RF1

Figure 54. Details of component values and PCB layout constraints can be found in Table 13.