Manualshelf

Data Sheet

ManualsBrandsNXP Laboratories UK ManualsElectronicsJN5142-001-M03 IEEE802.15.4 Wireless Module
51525354555657585960
© NXP Laboratories UK 2012 JN-DS-JN5142 1v0 51
SIF_CLK1
SIF_CLK2
SIF_CLK
Master1 SIF_CLK
Master2 SIF_CLK
Wired-AND SIF_CLK
Start counting
low period
Start counting
high period
Wait
State
Figure 37: Multi-Master Clock Synchronisation
After each transfer has completed, the status of the device must be checked to ensure that the data has been
acknowledged correctly, and that there has been no loss of arbitration. (N.B. Loss of arbitration may occur at any
point during the transfer, including data cycles). An interrupt will be generated when arbitration has been lost.