Data Sheet

15 Two-Wire Serial Interface (I

The JN5142 includes industry standard I

C two-wire synchronous Serial Interface operates as a Master (MSIF) or

Slave (SSIF) that provides a simple and efficient method of data exchange between devices. The system uses a

serial data line (SIF_D) and a serial clock line (SIF_CLK) to perform bi-directional data transfers and includes the

following features:

Common to both master and slave:

 Compatible with both I

C and SMbus peripherals

 Support for 7 and 10-bit addressing modes

 Optional pulse suppression on signal inputs

Master only:

 Multi-master operation

 Software programmable clock frequency

 Clock stretching and wait state generation

 Software programmable acknowledge bit

 Interrupt or bit-polling driven byte-by-byte data-transfers

 Bus busy detection

Slave only:

 Programmable slave address

 Simple byte level transfer protocol

 Write data flow control with optional clock stretching or acknowledge mechanism

 Read data preloaded or provided as required

The Serial Interface is accessed, depending upon the configuration, DIO14 and DIO15 or DIO16 and DIO17. This is

enabled under software control. The following table details which DIO are used for the Serial Interface depending

upon the configuration.

Signal

DIO Assignment

Standard pins

Alternative pins

SIF_CLK

SIF_D

Table 8: Two-Wire Serial Interface IO

15.1 Connecting Devices

The clock and data lines, SIF_D and SIF_CLK, are alternate functions of DIO15 and DIO14 respectively. The serial

interface function of these pins is selected when the interface is enabled. They are both bi-directional lines,

connected internally to the positive supply voltage via weak (45k) programmable pull-up resistors. However, it is

recommended that external 4.7k pull-ups be used for reliable operation at high bus speeds, as shown in Figure 35.

When the bus is free, both lines are HIGH. The output stages of devices connected to the bus must have an open-

drain or open-collector in order to perform the wired-AND function. The number of devices connected to the bus is

solely dependent on the bus capacitance limit of 400pF.